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| CXA3221AN RX Gain Control Amplifier Description CXA3221AN is an RX gain control amplifier suitable for CDMA cellular/PCS phone. Features * Wide gain control range * Linear gain slope * Wideband operation (50MHz to 300MHz) * Very small package (8 Pin SSOP) * Low voltage operation * Power save function included Absolute Maximum Ratings * Supply voltage VCC 6 V * Operating temperature Topr -55 to +125 C * Storage temperature Tstg -65 to +150 C * Supply voltage range -0.3 to 6 V * Logic input voltage -0.3 to VCC + 0.3 V * Signal input voltage -0.3 to VCC + 0.3 V * Differential signal input voltage 0 to 2.5 V Operating Condition Supply voltage Applications CDMA cellular/PCS phone Structure Bipolar silicon monolithic IC 8 pin SSOP (Plastic) VCC 2.7 to 3.8 V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E98910A8Y CXA3221AN Block Diagram IF Input for CDMA CDMA IN CDMA INX OUT OUTX IF Output Gain control GCTL Supply Voltage VCC Bias Driver Ground GND Power Save PSV Pin Configuration GND 1 8 GCTL CDMA IN 2 7 VCC CDMA INX 3 6 OUTX PSV 4 5 OUT -2- CXA3221AN Pin Description Pin No. 1 Symbol GND Pin voltage TYP (V) 0 VCC Equivalent circuit Ground. Description 2 CDMA IN 1.15 2k 2 3 2k Differential input pins for received CDMA IF signal. 3 CDMA INX 1.15 GND VCC 4 PSV -- 4 135k Power save function pin. High: Active Low: Power save GND VCC 460 460 12.3k 5 OUT -- 5 6 12.3k Differential output pins for received CDMA IF signal. Open collector output. 6 OUTX -- GND 7 VCC 3.0 VCC 8k 8k Positive power supply. 200 8 GCTL -- 8 Gain control pin. 6k 6k GND -3- CXA3221AN Electrical Characteristics DC Characteristics Parameter Current consumption 1 Current consumption 2 Input current pin 8H Input current pin 8L Input current pin 16H Input current pin 16L PSV high voltage PSV low voltage Symbol ICC1 ICC2 IpsvH IpsvL IgctlH IgctlL VpsH VpsL Conditions Vpsv = 3.0V, Vgctl = 1.5V, Pin 7 Vpsv = 0 V, Vgctl = 1.5V, Pin 7 Vpsv = 3.0V Vpsv = 0 V Vgctl = 3.0V Vgctl = 0.5V Pin 4 Pin 4 -1 2.5 0.5 V -15 1 (VCC = 3.0V, Ta = 27C) Min. Typ. Max. Unit 7 5 10.2 18 15 40 1 A mA AC Characteristics Parameter Operating frequency range Gain 2.4 Gain 1.5 Gain 0.6 Gain slope Input level 3rd order intercept point Noise Figure Symbol Fr G2.4 G1.5 G0.6 GCLIN IIP3 f = 210.38MHz, Vgctl = 2.4V Vgctl = 1.5V Vgctl = 0.6V Gain at Vgctl = 2.0V - Gain at Vgctl = 1.0V G = 40dB1 f1 = 209.38MHz, f2 = 211.38MHz Measure of 210.38MHz G = 40dB1 Measure of 210.38MHz Conditions (VCC = 3.0V, Ta = 27C) Min. Typ. Max. Unit 50 42 -7 -59 58 -42 46 -3 -55 61 -38 300 MHz 50 1 -51 64 dB/V dBm dB NF 5 8 dB 1 Adjust GCTL voltage, and set the overall gain to 40dB. -4- CXA3221AN Measurement Circuit 10k 1 GND GCTL 8 0.01 1000p 1 CDMA INPUT 2 1000p 180n 3 CDMA INX 2 CDMA IN VCC 7 A7 A8 V8 OUTX 6 1.6k 150n3 150n3 0.01 1 OUTPUT A4 4 PSV OUT 5 1 TOKO, Inc. B5FL 616DS-1135 2 Coilcraft, Inc. 0805HS-181TKBC 3 Coilcraft, Inc. 0805HS-151TKBC Application Circuit VCC 0.01 1k 1 GND 1000p 2 CDMA IN RX IF INPUT 3 CDMA INX 1000p Active Sleep 4 PSV OUT 5 OUTX 6 VCC 7 0.01 GCTL 8 100p Gain Control Voltage 1000p RX IF OUTPUT 1000p Must be adjusting values to result a best impedance matching between BPF filter and this IC. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. -5- CXA3221AN Design Reference Values Single ended measurement Item Input resistance Input capacitance Output resistance Output capacitance Symbol Rin Cin Rout Cout f = 210.38MHz, Vgctl = 1.5V Conditions (VCC = 3.0V, Ta = 27C) Typ. 1.6 1.3 5.9 0.73 Unit k pF k pF Notes on Operation 1) This IC is a wideband amplifier with wide gain control range. The decouping capacitors between GND Pin and VCC Pin should be as close to the IC as possible. 2) The resistors connected to Pins 5 and 6 should be as close to the IC as possible. 3) This IC assumes the excellent characteristics when the differential input impedance between Pins 2 and 3 is 500. Refer to the Measurement Circuit for the external element settings, etc. 4) Pay attention to handling this IC because its electrostatic discharge strength is weak. -6- CXA3221AN Sensitivity 60 VCC = 3.0V 40 20 -10 0 IIP3 VCC = 3.0V Power gain [dB] -20 0 -20 -40 -60 -80 0 0.5 1 1.5 Vgctl [V] 2 2.5 3 IIP3 [dBm] -30 -40 T = -40C T = 27C T = 85C T = -40C T = 27C T = 85C -50 -60 -80 -60 -40 -20 0 20 40 60 Power gain [dB] Noise Figure 25 VCC = 3.0V 20 4 6 Gain Error from Room Temp VCC = 3.0V Noise figure [dB] 15 Gain error [dB] T = -40C T = 27C T = 85C 0 10 20 30 40 50 60 2 0 10 -2 T = -40C T = 85C 5 -4 0 -10 -6 -80 -60 -40 -20 0 20 40 60 Power gain [dB] Power gain [dB] -7- CXA3221AN Package Outline Unit: mm 8PIN SSOP (PLASTIC) 3.0 0.1 + 0.2 1.25 - 0.1 0.1 8 5 A 4.4 0.1 1 4 0.65 + 0.08 0.24 - 0.07 B 0.25 0.13 M 0.1 0.05 6.4 0.2 (0.22) (0.15) + 0.025 0.17 - 0.015 + 0.08 0.24 - 0.07 0 to 10 DETAIL A DETAIL B NOTE: Dimension "" does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-8P-L01 SSOP008-P-0044 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER ALLOY 0.04g -8- (0.5) 0.6 0.15 |
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